MicroCloud Hologram Proposes Quantum AI Simulator, 500x Speed Increase
MicroCloud Hologram proposed a quantum AI simulator that adopts a hybrid CPU-FPGA method. This system performs hardware-level optimization on the specific structure of quantum kernels through a heterogeneous computing architecture, making quantum kernel estimation 500 times faster than traditional CPU simulation implementations under the same computational scale, providing unprecedented acceleration capabilities for the application simulation of quantum artificial intelligence. This technology of HOLO focuses on application-specific quantum kernels designed for image classification tasks, and for the first time implements its core computational process on a Field Programmable Gate Array. Through deep collaborative design of quantum kernel structures, feature encoding methods, and FPGA dataflow architectures, HOLO has constructed a hardware acceleration platform oriented towards quantum machine learning algorithms, enabling the simulation of quantum kernel models with high-dimensional feature encoding capabilities under classical computing resources. This achievement not only breaks through the physical qubit limitations faced by current noisy intermediate-scale quantum devices but also provides a new direction for future hardware-based quantum algorithm prototype verification. In terms of the specific construction of the quantum kernel, HOLO designed an empirical parameterized encoding strategy for image classification tasks. Image samples are first compressed into fixed-dimensional feature vectors, and then transformed into rotation angle parameters via nonlinear mapping to input into the quantum circuit. The quantum kernel circuit structure includes multiple layers of controlled rotation gates and entanglement gates, used to construct global feature correlations. Through experimental comparisons, it is obtained that appropriately increasing the quantum kernel depth can significantly improve classification performance, but it also leads to exponential growth in simulation complexity. Therefore, HOLO adopted a collaborative optimization strategy, namely restricting the entanglement range of the circuit at the algorithm level, while at the hardware level performing logic reuse and lookup table optimization on common gate operations to maximize hardware utilization. On this basis, the FPGA's logic resource utilization rate is maintained below 82%, and the on-chip storage bandwidth can support quantum state update operations for 256 parallel channels. To further verify the performance of the simulator, HOLO conducted tests on the system across multiple sets of image classification tasks, including the classic MNIST and Fashion-MNIST datasets. The experimental results indicate that the FPGA-accelerated quantum kernel estimation, under the same sample scale, has a runtime of only about 1/500 of the CPU implementation, and achieves classification accuracy comparable to the Gaussian kernel with optimized hyperparameters. This means that, through reasonably designed quantum kernel structures and efficient hardware acceleration mechanisms, HOLO can reproduce the core performance characteristics of quantum algorithms on classical hardware without relying on actual quantum hardware. More importantly, this simulation platform provides a practical and feasible channel for algorithm verification, model comparison, and scalability testing of quantum machine learning algorithms.
